Why multiple Triple Speed Ethernet Intel® FPGA IP instances with transceivers fail to fit into the same transceiver quadrant?

Description

It is due to the reason that the clock synchronizer for transceiver was added into the transceiver’s power-down input, causing the power-down input for each TSE transceiver block undriven by the same power-down input source.

Resolution

The following patch provides a solution to ensure power down signals into each IP TSE transceiver block is common.

Download the appropriate Quartus® II software version 10.1SP1 patch 1.77 from the following links:

• Quartus II software version 10.1SP1 patch 1.77 for Windows
• Quartus II software version 10.1SP1 patch 1.77 for Linux
• Quartus II software version 10.1SP1 ReadMe for patch 1.77

Caution:

You must either have installed the Quartus II 10.1 SP1 software previously or install the Quartus II 10.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.

After you have installed the patch, regenerate your Triple Speed Ethernet Intel® FPGA IP before you compile your design.