Knowledge Base Article
Why might my Stratix V PCIe Gen 2 design intermittently downtrain to Gen1 speed?
Description
Due to a bug in the Quartus® II software you may experience your Stratix® V PCIe® Gen 2 design downtrain from Gen 2 to Gen 1.
This issue affects Stratix V devices only and versions of Quartus II software up to and including version 12.0 SP2.
Resolution
To workaround this issue, upgrade to Quartus II software version 12.0 SP2, then download and install Device Patch 2.dp5 or greater from the related solution below.
As outlined in the Readme file for this Device Patch, you will need to perform the following steps to successfully apply this solution:
1. Add the following QSF settings:
set_instance_assignment -name XCVR_RX_SD_ON 1 -to <rx_serial_pin name>
set_instance_assignment -name XCVR_RX_SD_OFF 5 -to <rx_serial_pin name>
set_instance_assignment -name XCVR_RX_SD_THRESHOLD 4 -to <rx_serial_pin name>
set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE VTT_0P70V -to <rx_serial_pin name>
2. The PHY IP reconfiguration controller must be connected to the PCIe IP
G1/G2 : Use offset cancellation ON
3. Regenerate the PCIe IP
4. Recompile the design
This issue is schedule to be fixed in a future release of Quartus II software.
Related solution:
http://www.altera.com/support/kdb/solutions/rd08232012_334.html