Why might I see transmission errors when running a single lane SerialLite III IP core implementation on Intel® Stratix® 10 FPGA hardware?

Description

You might see Transmission Error when running a single lane SerialLite III IP core implementation on Intel® Stratix® 10 FPGA on hardware if Required idle cycles between bursts parameter value is set to 2.

Resolution

To work around this problem, change Required idle cycles between bursts value to 1. Regenerate and recompile.

This problem is scheduled to be fixed in the next full production release of the Intel® Quartus® Prime Pro Edition Software.