Why is Xcelium* (VHDL and Verilog) simulation failing for the F-tile Dynamic Reconfiguration Suite IP designs?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may see Xcelium* (VHDL and Verilog) simulation failure with error “always_ff process requires one and only one event control” for the F-tile Dynamic Reconfiguration Suite Intel FPGA IP designs with the following configurations: 

1. ) Ethernet 25G RS-FEC with PTP, 
2. ) 100G RS-FEC with PTP, 
3. ) 400G RS-FEC with PTP  
4. ) Ethernet to CPRI supported PTP version 25G-1 RS-FEC with PTP
    

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1.