Why is timing not closing in my Stratix V Hard IP for PCI Express on Quartus 13.1?

Description

Timing may not closing in the Stratix® V Hard IP for PCI® Express because constraints are missing on internal clocks that are in separate domains.

Resolution

The missing constraints can be added to your top level Synopsis Design Constraint (sdc) file as below:

set_false_path -from [get_clocks {reconfig_xcvr_clk}]  -to [get_clocks {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]
set_false_path -from [get_clocks {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]  -to  [get_clocks {reconfig_xcvr_clk}]