Why is there a mismatch in the MSI-X Table and Pending Bit Array (PBA) Offsets between the IP Parameter values and offset values observed on hardware for the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express*?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 21.4 or earlier, the MSI-X Table offset, and Pending bit array (PBA) offset parameters set in the IP Parameter editor do not reflect the actual vector table offsets seen in the hardware.

For example, a Table Offset of 0x003FFC00 set in the IP Parameter editor will be reported as 0x01FFE000 in hardware, and a PBA offset set to 0x03FFE00 in the IP Parameter editor will be reported as 0x1FFF000 on hardware.

Resolution

To workaround this problem, set the MSI-X IP parameters in the IP Parameter editor according to the following guidelines:

• The Table Offset field in the IP Parameter editor sets bits [31:3] of the desired Table offset
• The Table BAR Indicator field in the IP Parameter editor sets the lower three bits [2:0] of the table offset
• The Pending Bit Array (PBA) field in the IP Parameter editor sets bits [31:3] of the PBA offset in hardware.
• The PBA BAR indicator in the IP Parameter editor sets the lower three bits [2:0] of the PBA offset in hardware.

For example, if you want the Table offset to be 0x003F_FC00, set the Table Offset parameter to 0x0007_FF80 (Table Offset [31:3]) and the Table BAR Indicator parameter to 0x0 (Table Offset [2:0]).

This problem will be fixed in a future version of the Quartus® Prime Pro Edition Software.

 

 

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