Why is the "[VITAL_NO_PORT_ON_TGEN] Missing port association" warning flagged in VHDL simulation for GTS AXI Streaming IP for PCI Express*?

Description

The warning message exists because a generic timing signal "tpd_datainglitch_dataout" is used without a port driving it.  

This warning can be safely ignored during simulation. 

Resolution

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.