Why is the unexpected Assertion or Toggling of the "rx_ready" port on the FGT transceiver of the F-Tile PMA/FEC Direct PHY FPGA IP observed in the Quartus® Prime Pro edition software version 24.3.1?

Description

The rx_ready port on the FGT transceiver of the F-Tile PMA/FEC Direct PHY FPGA IP, when the Adaptation Mode is set to “Manual”, may assert or toggle unexpectedly under the following conditions:

1. Invalid data on the RX pins from the link partner
2. Unconnected RX pins
3. During link bring-up

Resolution

When using the FGT transceiver of the F-Tile PMA/FEC Direct PHY FPGA IP with Adaptation mode set to "Manual", be aware of the potential behavior of the "rx_ready" port. If the "rx_ready" port asserts and then deasserts, your protocol logic must properly return to its initial state and wait for the next assertion of "rx_ready" to process data on the "rx_parallel_data" bus again.