Why is the sys_error signal asserted high when using the Advanced SEU Detection Intel® FPGA IP in Intel® Stratix® 10 and Intel Agilex® 7 FPGA devices

Description

Due to a problem in Intel® Quartus® Prime Pro Edition Software version 20.4 and above, you will observe the sys_error signal asserted high in Signal Tap Logic Analyzer as shown below when using the Advanced SEU Detection Intel® FPGA IP in Intel® Stratix® 10 and Intel Agilex® 7 FPGA devices.

 

The expected response of the sys_error signal should be low.    

 

 

Resolution

This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 21.3.