Why is the simulation result of the "demo_cfr" in the DSP Builder for FPGAs incorrect?

Description

Due to a problem with the DSP Builder for FPGAs in the Quartus® Prime Pro Edition Software v20.4, the .mdl simulink file only works for one specific device/speedgrade/clock target combination. The simulation results will be wrong with other combinations.

Resolution

To workaround this problem, replace the old .mdl simulink file in demo_cfr with the new demo_cfr.mdl file.