Why is the pll_powerdown port of the Intel® Stratix® V device Transceiver Native PHY IP Core not removed when I enable the “Use external TX PLL” option?

Description

Due to a problem in the Quartus® II software, the pll_powerdown port of the Stratix® V device Transceiver Native PHY IP Core is not removed when the “Use external TX PLL” option is enabled. This pll_powerdown port is not connected to any submodule, and you can connect it to '0' in your design.

Resolution

This pll_powerdown port is not connected to any submodule, and you can connect it to '0' in your design.