Why is the phase_done deassertion inconsistent in RTL simulation?

Description

When using dynamic phase stepping in the Altera_PLL mega function, you may see different behavior for the de-assertion of the phase_done output signal in RTL simulation.

The correct behavior is for phase_done to de assert on the rising edge of scanclk as stated in AN 661: Implementing Fractional PLL Reconfiguration with Altera_PLL and Altera_PLL_RECONFIG Megafunctions (PDF).

However, in RTL simulation, you may see phase_done de assert at the falling edge of scanclk.  This typically occurs only in the first phase step operation.  This is a problem in the RTL simulation model.

Resolution

This issue with the RTL simulation model is fixed in version 13.1 of the Quartus® II software.