Why is the nINIT_DONE signal always stuck in a HIGH state when using the Reset Release Intel® FPGA IP in all Intel Agilex® devices?

Description

Due to a problem with the Reset Release Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software version 20.3 and earlier, the nINIT_DONE signal is always stuck in a HIGH state when using all Intel Agilex® devices.

Resolution

To fix this problem, recompile the design in the Intel® Quartus® Prime Pro Edition Software starting from version 20.4.

The Intel® Quartus® Prime Pro Edition Software version 20.4 allows the SOF generated from software version 20.3 and below to program into all Intel Agilex® FPGAs. However, the Intel® Quartus® Prime Pro Edition Software will report a critical warning message if you try to program the SOF generated from version 20.3 and below through a command line. The following critical warning message will not be reported if you use the Intel® Quartus® Prime Software Programmer.

Critical Warning: The SOF provided is generated using Intel® Quartus® Prime Pro Edition software version 20.3 and below. Kindly recompile the design on Intel® Quartus® Prime Pro Edition software version 20.4 and above. Using SOF generated in Intel® Quartus® Prime Pro Edition software version 20.4 and above will cause the output of the Reset Release Intel® FPGA IP to behave abnormally.