Why is the input data rate parameter text box not present in the ALTLVDS_RX Intel® FPGA IP in the Quartus® II software version 13.0sp1?

Description

In the Quartus® II software version 13.0, the input data rate text box was available when using external phase-locked lioop (PLL) mode with DPA enabled in the ALTLVDS_RX Intel® FPGA IP.

Resolution

Beginning with version 13.0sp1, the fitter automatically derives the data rate from the associated PLL Intel FPGA IP settings.