Why is the HPS clock not reflected in the handoff file when exporting peripherals to FPGA is enabled?

Description

Due to a problem with Intel® Quartus® Prime Pro Edition Software, starting version 19.4,  the handoff files may not properly be created by Platform Designer.

This problem can be observed in designs that include an Intel Agilex® 7 device and when exporting peripherals to the FPGA fabric.

Resolution

 To workaround this issue, go inside the Intel® Quartus® Platform Designer tool,  Instantiate the HPS IP component, and apply the following changes:

1.     Go to Pin Mux, and Peripherals --> Advanced --> Advanced IP Placement and add HPS IO, including HPS clock, click Apply Selections

                                                                            

2.    Go to Pin Mux and Peripherals --> Advanced --> Advanced FPGA Placement and add export FPGA (for example, SPI Master) and click Apply Selections

                                                                    

3.    Go back to Pin Mux, and Peripherals --> Advanced --> Advanced IP Placement and click Apply Selections again

                                                                            

* Step 3 above must be done every time a user modifies the Advanced FPGA Placement page for proper handoff files to be created and peripheral operation to occur.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.