Why is the Function Level Reset request being ignored or not processed by the GTS AXI Streaming FPGA IP for PCI Express*?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, back-to-back Function Level Reset requests with intervals less than 16 axi_st_clk clock cycles may not be handled correctly by the GTS AXI Streaming FPGA IP for PCI Express*.

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.2.