Why is the eCPRI Intel® FPGA IP reset polarity inverted in platform designer?

Description

Due to a problem in the eCPRI Intel® FPGA IP version 2.0.4 and earlier, the input reset signal maps to incorrect polarity when instantiated in Platform Designer. The input reset to the eCPRI Intel® FPGA IP is active low, Platform Designer should automatically map the signal type to "reset_n" instead of reset.

Resolution

To work around  this problem,  perform the following steps:

1). Open the ecpri_interface.tcl file available at <quartus_instalation_dir>/ip/altera_cloud/ecpri/ecpri_hw_tcl/.

2). Find and replace the following line: 

     From add_interface_port $port_name $port_name reset input 1
     To add_interface_port $port_name $port_name reset_n input 1

This problem has been fixed starting in version 23.3 of the eCPRI Intel® FPGA IP webcore.