Why is the default transceiver reference clock timing constraint of Serial Digital Interface (SDI) IP core set to 74.5 MHz when HD-SDI two times over sample option is selected?

Description

Due to a problem in the Quartus® II software, the default transceiver reference clock timing constraint for the Serial Digital Interface (SDI) IP core is incorrectly set to 74.5 MHz when HD-SDI Two times oversample mode is selected. The correct transceiver reference clock frequency is 148.5 MHz or 148.35 MHz as described in the user guide (PDF).

Resolution

To work around this problem, follow the procedures below.

1. Open the <variation name>_sdi.sdc file with a text editor
2. Find the create_clock constraint for the transceiver reference clock

    create_clock -name -period 13.468 -waveform { 0.000 6.734 } [get_ports ]

3. Change the period from 13.468 to 6.734
4. Change the fall time from  6.734 to 3.367

    create_clock -name -period 6.734 -waveform { 0.000 3.367 } [get_ports ] 

This problem is scheduled to be fixed in a future version of the Quartus II software.