Why is the data word alignment behavior of my altlvds_rx different between simulation and hardware?

Description

Due to inaccuracies in the LVDS SERDES simulation model, the number of pulses applied to rx_channel_data_align to achieve data word alignment may differ between simulation and actual hardware.

Resolution

For more details, see the Aligning Word Boundaries section of the LVDS SERDES Transmitter/Receiver IP Cores User Guide.

To work around this problem, do the following:

1. Simulate your design with a known data word and find the number of pulses applied to rx_channel_data_align to achieve data word alignment.  Use this number as the simulation value for your data word alignment state machine.  You can do this in a verilog #define or in VHDL, a generic with an if - generate statement.  
2. In lab testing, apply a known data word and apply successive pulses to rx_channel_data_align to find data word alignment.  Use the number of pulses found to achieve data word alignment as the synthesis value in your #define or if -generate statement.