Why is the byte order reversed in simulation for mixed-width dual-port memories?

Description

Due to a problem in the Quartus® II software version 13.0 and earlier, the byte order for mixed-width dual-port memories may be reversed between RTL and gate-level simulation. This problem can occur when inferring a memory in your RTL code.

Resolution

To work around this problem, modify your RTL code so that the memory variable is arranged from high to low instead of low to high.

For example, if you have the memory declaration as below in your RTL code:

type ram_type1 is array (0 to DEPTH-1) of std_logic_vector((DATA_WIDTH -1) downto 0);

Change to the following:

type ram_type1 is array (DEPTH-1 downto 0) of std_logic_vector((DATA_WIDTH -1) downto 0);

This issue is scheduled to be fixed in a future release of the Quartus II software.