Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller?

Description

Due to a problem in the Quartus® II software version 12.1 and later, UniPHY-based memory controllers are missing SDC constraints to properly constrain the afi_half_clk clock leading to incorrect timing analysis for the afi_half_clk clock domain.

Resolution

If the design is not using the afi_half_clk signal, no changes need to be made.

If the design uses the afi_half_clk signal, add a create_generated_clock assignment for afi_half_clock to the top-level SDC file.

If there is no top-level SDC file, create one and add it to the project file list.

This issue has been fixed in Intel® Quartus® Prime Edition Software version 13.1