Why is no video output displayed when migrating the F-Tile SDI II FPGA IP Design Example with 12G multi-rate from an older version to Quartus® Prime Pro Edition Software version 25.3.1 patch 1.10 ?

Description

Due to an issue in the Quartus® Prime Pro Edition Software Programmer version 25.3.1, users may observe that no SDI II video output is displayed on the receiver side when using the F-tile SDI II FPGA IP Design Example with 12G multi-rate on Agilex® 7 FPGA devices.

This issue is caused by forcing lock-to-data. For SDI dynamic reconfiguration designs, manual CDR lock mode with lock-to-ref enabled should be used.

Resolution

To solve this problem, use below method

1. Open Platform Designer of sdi_rx_sys.qsys

2. Disable fgt_rx_set_locktodata port, Enable fgt_rx_set_locktoref port 

3. At System View

• • Should not seeing fgt_rx_set_locktodata port 
  • Export fgt_rx_set_locktoref port out
  • 

4. Sync info and regenerate HDL

5. Open rx_top.sv file

• • Comment out / remove fgt_rx_set_locktodata
  • Add exported fgt_rx_set_locktoref port and connect to ~rx_set_ltd
  • 

     

6. Save and recompile design

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.