Knowledge Base Article

Why is my Arria V QDR II and QDRII SRAM controller with UniPHY IP missing a CQn clock signal ?

Description
The Arria® V architecture does not support a complementary CQ clock. Instead, both edges of the CQ clock are used to capture the read data.
Updated 2 months ago
Version 2.0
arria® v fpgas and socs
troubleshooting
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