Why is mgmt_clk missing from the Stratix V Hard IP for PCI Express port list?

Description

The mgmt_clk signal is not a required input to the Stratix® V Hard IP for PCI Express®  hard IP and only needs to be connected to the reconfiguration controller.

The mgmt_clk is embedded within the reconfig_toxcvr interface that connects to the PHY IP Core for PCI Express, hence the interface remains synchronous. This has made the interconnect between the reconfiguration controller and the PHY IP simpler to use.