Why is IRQ not automatically cleared to 0 in single cycle conversion mode when simulating the MAX 10 ADC IP Core?

Description

The EOP bit in the ISR register of the Modular ADC IP Core in MAX® 10 devices, which is responsible for generation of IRQ, is set to ‘1’ by hardware when a complete block of samples is received. This bit does not automatically clear to 0 in RTL simulation. Users need to write 1 to this bit in order to clear it.

Resolution

To clear this EOP bit to 0 for the next interrupt, write 1 to ISR register to indicate that a complete block of samples is received.