Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1?

Description

Due to a problem in the Intel® Stratix® 10 Hard IP for PCI Express* IP Core version 18.1, you may observe a minimum pulse width timing violation information message during compilation.

Resolution

This message can be safely ignored.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.1.