Why is a global signal assignment to |s0|rst_controller|alt_rst_sync_uq1|reset_out being ignored by my UniPHY-based DDR3 controller IP?

Description

After the UniPHY-based DDR3 IP pin_assignments.tcl script is run and the project compiled, the Quartus® II software Ignored Assignments Fitter report incorrectly shows a global signal assignment to the reset signal <instance_name>|s0|rst_controller|alt_rst_sync_uq1|reset_out.

Resolution

This ignored global assignment is due to a legacy code assignment and can be ignored. 

This problem is fixed starting with the Quartus® II software version 14.1.