Why HPS hangs when HPS to FPGA bridge is connected to AXI Bridge IP together with other bus master(s)?

Description

HPS may hang while accessing to AXI Bridge which is interfaced with more than one bus master.

AXI Bridge slave interface will constantly back-pressure master access when one of the master issues read/write transactions to it.

Resolution

As temporary workaround, add an Avalon MM Pipeline Bridge in between the bus masters and the AXI Bridge to resolve AXI Bridge multiple master signals handling issue.