Why have the IO_PLL_REFCLK pins been removed in the Intel Agilex® FPGA Pin Connection Guidelines?

Description

In the Intel Agilex® FPGA Pin Connection Guidelines and the pinout file from Intel® Quartus® Prime Software, you will notice IO_PLL_REFCLK_[12A,12C,13A,13C]_GXF has been removed.

Resolution

This is due to the use of an Intel® Quartus® Prime Software that uses an Intel® Internal IP. Intel recommends you connect this pin to the ground through a 0 Ohm resistor.