Why don't the IOPLL output clocks operate as expected when using Advanced Mode reconfiguration following table 18 in the Intel Agilex® 7 FPGA Clocking and PLL User Guide?

Description

Due to a problem in the Intel Agilex® 7 FPGA Clocking and PLL User Guide (UG-20216) version 2021.06.21, the address map for C1-C7 counters in table 18 is incorrect.

Therefore, if you follow the address map in table 18, the IOPLL output clocks will not output the correct clocks as expected.

Resolution

To work around this problem, follow the address setting and C Counter Mapping as shown in the following table.

Output Clock	C Counter	High Count	Low Count	Bypass Enable	Odd Divison
outclock0	C1	00011111	00100010	00100000	00100001
outclock1	C2	00100011	00100110	00100100	00100101
outclock2	C3	00100111	00101010	00101000	00101001
outclock3	C4	00101011	00101110	00101100	00101101
outclock4	C5	00101111	00110010	00110000	00110001
outclock5	C6	00110011	00110110	00110100	00110101
outclock6	C7	00110111	00111010	00111000	00111001

This problem is fixed starting with the release of the Intel Agilex® 7 FPGA Clocking and PLL User Guide version 2022.11.09.