Why doesn't the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express reconfiguration interface access the configuration space registers?

Description

For the application logic to access the configuration space registers, use the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express with TLP BYPASS mode, Hard IP reconfiguration interface.

The Hard IP reconfiguration interface cannot be used when the debug toolkit is enabled.

 

Resolution

Ensure that the debug toolkit option is disabled when using the Hard IP reconfiguration interface.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.