Why doesn't Quartus II synthesis recognize my SystemVerilog state machine?

Description

In the Quartus® II software, if you use an enum type for your state variable in your SystemVerilog design file, this defaults to a signed int type. Quartus II synthesis does not recognize this as a state machine. Only unsigned int types are recognized as state variables by Quartus II synthesis.

Resolution

Define your enum type as an unsigned int, for example:

enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state;