Why doesn't pulsing transceiver edge sensitive input signals have an effect in Cyclone V, Arria V and Stratix V transceiver devices?

Description

When driving the Cyclone® V, Arria® V and Stratix® V device transceiver edge sensitive signals, such as the rx_std_wa_patternalign signal, you must still comply with the minimum pulse width requirement. The minimum typical pulse width is two parallel clock cycles.

Resolution