Why doesn't assertion of the pll_powerdown input signal reset the Intel® Arria® 10 device fPLL?

Description

By default, the Intel® Arria® 10 fPLL IP core's internal reset signal is controlled by the Avalon-MM register but not the pll_powerdown input signal. Therefore, asserting the pll_powerdown input signal will not reset the Intel® Arria® 10 fPLL.

Resolution

Add the following QSF assignment to change the reset control from the Avalon-MM register to the pll_powerdown input:        

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS=1"