Why doesn’t the capture phase of the EXTEST instruction capture the correct data values for the my MAX® 7000S device I/O pins during JTAG boundary-scan testing?

Description

During Joint Test Action Group (JTAG) boundary-scan testing, the capture phase of the EXTEST instruction mode does not capture correct data values for the input boundary-scan registers of the I/O pins. Therefore, the TDO output shifts out incorrect data valuesùbsp;this case, all "0"s in the locations corresponding to the input boundary-scan registers. The output and output enable boundary-scan registers do capture the correct data values. This problem does not affect dedicated input pins or any other JTAG boundary-scan test (BST) instruction modes.                                                            
                                                                              

The affected revisions of silicon are:                                 

• EPM7128S-10/15    Revision A                                                
• EPM7128S-7          Revisions A thru F                                        
• EPM7192S             Revisions A and B                                         
• EPM7256S             Revision A        

All other silicon revisions are not affected by this problem. 

You can use one of the following two solutions to work around this  problem. The first solution should meet most testing needs. The second solution requires more work; however, it allows all traces to be tested.            
                                                                              
Solution 1                                                             
                                                                              
Ensure that the MAX 7000S device is always the source and the "other" device is the destination. This solution works provided any one device connected to the trace is a non-MAX 7000S device.                             
                                                                              
Solution 2                                                             
                                                                              
If only MAX 7000S devices are connected to the trace, the capture phase  of the SAMPLE/PRELOAD instruction can be used. The Sample/Preload instruction is typically used to capture data during normal operation. Therefore, the device must first be programmed with a design that does not interfere with testing by performing the following steps:                                                                                 

1. Create a test design for device A. All the pins in this design should  be tri stated.                                                                                                                                            
2. Program device A with the test pattern.                                                                                                           
3. Drive signals using EXTEST mode from device B (source) to device A         
   (destination) in SAMPLE/PRELOAD mode. Device B can be programmed with  any pattern. 

For additional JTAG operation information, go to AN 39 (JTAG  Boundary-Scan Testing in Altera Devices), which is available from the following sources:  

• site (http://www.altera.com)                                                                         
• Altera FTP site (ftp.altera.com)               
• Altera Bulletin Board Service at (408) 954-0104                           

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• What is EXTEST mode?