Why does tx_ready stuck low when using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP?

Description

When using the F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP with Fiber Channel RSFEC enabled, you may see tx_ready stuck low after triggering tx_reset. 

Resolution

Although alignment marker is not needed when using RSFEC with Fiber Channel mode. You must still give  tx_am_gen_2x_ack by counting tx_clkout cycles to complete the SRC handshake. Then tx_ready will go high after the handshake is complete. This note will be updated in a further release of the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.