Why does the Triple Speed Ethernet IP Core have timing violations from node in_data_buffer[*] to out_data_buffer[*]?

Description

Some Triple Speed Ethernet IP Core variants are missing the required SDC constraints for clock domain crossing adaptors and this can cause timing violation be seen.
The affected Triple Speed Ethernet variants are with the following options enabled:

· Core variation: 10/100/1000Mb Ethernet MAC, AND
· NOT include statistics counters, AND
· Either of the following options is enabled:
 - MAC 10/100 half duplex support
 - ECC protection
 - Timestamping

Example of violation path:

FROM
top_module:u0|top_module_eth_module:eth_module|top_module_eth_module_eth_tse_1:eth_tse_2|altera_eth_tse_fifoless_mac:i_tse_fifoless_mac_0|altera_tse_top_wo_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_wo_fifo:U_MAC|altera_tse_ptp_1588_tx_top:U_PTP_TX|altera_tse_clock_crosser:clock_crosser_period_adjust|in_data_buffer[24]

TO:
top_module:u0|top_module_eth_module:eth_module|top_module_eth_module_eth_tse_1:eth_tse_2|altera_eth_tse_fifoless_mac:i_tse_fifoless_mac_0|altera_tse_top_wo_fifo_10_100_1000:U_MAC_TOP|altera_tse_top_wo_fifo:U_MAC|altera_tse_ptp_1588_tx_top:U_PTP_TX|altera_tse_clock_crosser:clock_crosser_period_adjust|out_data_buffer[24]

Resolution

Generate the Triple Speed Ethernet IP core with statistics counters enabled (checked the option 'Include statistic counters').

This issue is scheduled to be fixed in Quartus® software version 16.0.2.