Why does the Stratix V Advanced Systems Development Kit fail to link up to L0?

Description

Due to an error in the schematic, provided .pin and Quartus® II Settings File(.qsf) files, the PCI Express® reference clock is not assigned to the correct pins. This error prevents the link from reaching L0 and device enumeration.

Resolution

Please change the assignment of the refclk pin to AK38/AK39 instead of the incorrect AH39/AH40. The device will then link up to L0 and will enumerate correctly.