Why does the 'Size' parameter for the BAR0 to BAR5 is set to 4 by default in the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.0?

Description

Due to a problem in the Intel® Arria® or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.0, the 'Size' parameter for BAR0 to BAR5 is read only and set to 4 by default.

Resolution

To work around this problem, migrate your design to the Intel® Arria® or Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* version 18.1.