Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail when the vertical timing (Vtotal) parameter is modified?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and 25.3, simulation of the MIPI DSI-2 FPGA IP Design Example will fail if vertical timing parameters (VTOTAL) are modified.
This problem occurs because the simulation environment is fixed for a 96-line vertical active region (VTOTAL – VB_END), which causes mismatches with other configurations.
Horizontal timing changes work as long as the parameters remain consistent. This problem affects simulation only; the synthesized IP accepts any valid vertical timing configuration.

Additionally:

1. V1B_START must remain at line 0. Changing this parameter results in incorrect output.
2. When modifying vertical timing, ensure:
   • The active region ends at VTOTAL – 1.
   • Adjust V1B and V1S based on blanking starting at line 0.
   • This issue affects both simulation and synthesis of the IP.

Resolution

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.