Why does the simulation for F-Tile Ethernet FPGA Hard IP Design Example hang when 25G Ethernet mode and RS-FEC are enabled?

Description

Due to a problem in the Quartus® Prime Pro Edition Software Version 22.3, the simulation for F-Tile Ethernet FPGA Hard IP Design Example will hang when 25G Ethernet mode and RS-FEC are enabled.

Resolution

There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.