Why does the Serial Lite III Streaming FPGA IP design VHDL simulation fail using QuestaSim and Questa*- FPGA Edition Software?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, you might observe VHDL simulation failures for the Serial Lite III Streaming IP design with Standard Clocking Mode for the Stratix® 10 L/H-tile devices when using the latest version of QuestaSim and Questa*- FPGA Edition Software.

Resolution

To avoid this simulation failure, you can use the previous Questa Simulator version 2022.1.

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.