Why does the SDI II FPGA IP Design Example fail to generate when selecting the board option to Custom Development Kit?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the following error will appear when generating SDI II FPGA IP Design Example when  selecting the board option to Custom Development Kit:

Tcl error: ERROR: Value "OSC_CLK_1_" for "DEVICE_INITIALIZATION_CLOCK" assignment is illegal. Specify a legal value.

Resolution

To work around this problem, please follow the following steps below:

For Agilex™ 7 Device:

Users can select the No Development Kit option instead of Custom Development Kit.
The design generated will remain the same, but the user must update the PIN assignment in the QSF file.

For Stratix® 10 Device : 

Users can select the No Development Kit option instead of Custom Development Kit.
The user is required to update the PIN assignment and include the following assignment in the QSF file:

set_instance_assignment -name IO_STANDARD "1.8 V" -to <destination>

set_instance_assignment -name CURRENT_STRENGTH_NEW DEFAULT -to <destination>

set_instance_assignment -name SLEW_RATE 1 -to <destination>

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.1.