Why does the Scatter-Gather DMA Controller Core (SG-DMA) treat all data as big endian?

Description

Regardless of the data width set for the DMA, all byte lanes from a memory-mapped to streaming or streaming to memory-mapped transfer will be reversed.  The SGDMA assumes that 8 bit symbols are being transfer and performs the appropriate symbol reversing as a result.

 

If you do not wish for this symbol reversal to occur you can insert your own adapter component into the data path that reverses each byte lane.  For example if the data is 32 bits wide you could perform the following adaptation:

 

data_out[31:24] <-- data_in [7:0]

data_out[23:16] <-- data_in [15:8]

data_out[15:8] <-- data_in [23:16]

data_out[7:0] <-- data_in[31:24]

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