Knowledge Base Article

Why does the rx_st_bardec signal fail to assert for my Stratix V PCI Express Root Port implementation?

Description

The rx_st_bardec output signal is not working correctly for Root Port variants of the Stratix® V Hard IP for PCI Express IP® Core. The rx_st_bardec signal fails to assert for first data cycle of MRd, MWr, IOWR and IORD TLPs when the address of the TLP matches the address range of a BAR.

Resolution
The workaround is to implement the BAR decoding logic for Root Ports in user logic to determine which BAR (BAR0 or BAR1) is a TLP target. You can determine the BAR settings from your Root Port\'s Configuration Software. Alternatively, you can also determine the settings by decoding the Type 0 Configuration Writes that the Root Port sends on Avalon-ST to set up the BAR registers in the Root Port.
Updated 20 days ago
Version 2.0
FPGA Dev Tools Quartus II Software
Stratix® V FPGAs
troubleshooting
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