Why does the rx_block_lock signal of the F-Tile Ethernet Intel® FPGA Hard IP get stuck low when simulating using the the Aldec* Riviera* Verilog simulator in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier ?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the rx_block_lock signal of the F-Tile Ethernet Intel® FPGA Hard IP gets stuck low when simulating using the the Aldec* Riviera* Verilog simulator.

Resolution

There is no workaround for this problem.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.