Why does the RSU update cause the HPS to hang in Stratix® 10 FPGA devices with bitstreams containing large fabric designs from Quartus® Prime Pro version 25.1.1 and earlier?

Description

Due to a problem in the calculation of a timeout value by the System Design Manager (SDM) firmware during the Remote System Update (RSU) process in Stratix® 10 FPGA devices, the Hard Processor System (HPS) hangs because of an SDM timeout expiration. The timeout is determined by multiplying the fabric design size in the bitstream by 10,000 and storing the result in a 32-bit variable. For large fabric designs, this value exceeds the 32-bit limit, causing it to wrap around to a smaller number. This leads to a short timeout value, and therefore a timeout expiration. The problem occurs in the FPGA Configuration First boot mode and affects Quartus® Prime Pro Edition releases 25.1.1 and earlier with bitstreams from those releases.

Resolution

There is no workaround available for this problem. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software