Why does the register csr_sysref_singledet not get cleared after SYSREF detection in the JESD204C Intel® FPGA IP?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.2, in a single SYSREF generation subclass 1 system, the JESD204C Intel® FPGA IP will not enter the user phase because it is waiting for csr_sysref_singledet deassertion. 

Resolution

To work around this problem, follow these steps:

1. After the SYSREF pulse generation, assert csr_cgs_bypass_sysref to enter user phase manually.

 2. Send another SYSREF pulse. 

This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software v19.3