Why does the refclk_fgt_enabled_[n] signal on the F-Tile Reference and System PLL Clocks FPGA IP not function as expected in Quartus® Prime Pro Edition Software version 23.2?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, the refclk_fgt_enabled_[n] output signal on the F-Tile Reference and System PLL Clocks FPGA IP will always be 1’b0 when you enable monitor mode by setting en_refclk_fgt_[n][1..0] as 2’b11.  The refclk_fgt_enabled_[n] signal only functions when the en_refclk_fgt_[n] signal is set to 2’b00 (Disable REFCLK) or 2’b01 (Enable REFCLK).

Resolution

You should not set the en_refclk_fgt_[n][1..0] signal to 2’b11. If you want to monitor the status of your F-Tile FGT transceiver reference clock, you can infer this by monitoring the tx_pll_locked signal of F-Tile PMA/FEC Direct PHY FPGA IP

This problem is fixed in the Quartus® Prime Pro Edition software version 23.3.