Why does the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example report timing violation when selecting PLD clk frequency as 475Mhz?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the R-Tile FPGA IP for Compute Express Link* (CXL*) Type2 Design Example might report timing violation when selecting PLD clk frequency as 475MHz.

Resolution

This problem has no plan to be fixed in the future release of the Quartus® Prime Pro Edition Software.